mirror of
https://gitlab.com/ryzen-controller-team/ryzen-controller.git
synced 2024-12-23 02:23:31 +07:00
61 lines
1.9 KiB
C
61 lines
1.9 KiB
C
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/* SPDX-License-Identifier: LGPL */
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/* Copyright (C) 2019 Jiaxun Yang <jiaxun.yang@flygoat.com> */
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/* RyzenAdj API */
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#ifndef RYZENADJ_H
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#define RYZENADJ_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "nb_smu_ops.h"
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#ifdef _WIN32
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#define EXP __declspec(dllexport)
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#define CALL __stdcall
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#else
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#define EXP
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#define CALL
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#endif
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#define RYZENADJ_VER 5
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typedef struct {
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nb_t nb;
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pci_obj_t pci_obj;
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smu_t mp1_smu;
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smu_t psmu;
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} *ryzen_access;
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EXP ryzen_access CALL init_ryzenadj();
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EXP void CALL cleanup_ryzenadj(ryzen_access ry);
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EXP int CALL set_stapm_limit(ryzen_access, uint32_t value);
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EXP int CALL set_fast_limit(ryzen_access, uint32_t value);
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EXP int CALL set_slow_limit(ryzen_access, uint32_t value);
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EXP int CALL set_slow_time(ryzen_access, uint32_t value);
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EXP int CALL set_stapm_time(ryzen_access, uint32_t value);
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EXP int CALL set_tctl_temp(ryzen_access, uint32_t value);
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EXP int CALL set_vrm_current(ryzen_access, uint32_t value);
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EXP int CALL set_vrmsoc_current(ryzen_access, uint32_t value);
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EXP int CALL set_vrmmax_current(ryzen_access, uint32_t value);
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EXP int CALL set_vrmsocmax_current(ryzen_access, uint32_t value);
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EXP int CALL set_psi0_current(ryzen_access, uint32_t value);
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EXP int CALL set_psi0soc_current(ryzen_access, uint32_t value);
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EXP int CALL set_max_gfxclk_freq(ryzen_access, uint32_t value);
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EXP int CALL set_min_gfxclk_freq(ryzen_access, uint32_t value);
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EXP int CALL set_max_socclk_freq(ryzen_access, uint32_t value);
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EXP int CALL set_min_socclk_freq(ryzen_access, uint32_t value);
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EXP int CALL set_max_fclk_freq(ryzen_access, uint32_t value);
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EXP int CALL set_min_fclk_freq(ryzen_access, uint32_t value);
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EXP int CALL set_max_vcn(ryzen_access, uint32_t value);
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EXP int CALL set_min_vcn(ryzen_access, uint32_t value);
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EXP int CALL set_max_lclk(ryzen_access, uint32_t value);
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EXP int CALL set_min_lclk(ryzen_access, uint32_t value);
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#ifdef __cplusplus
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}
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#endif
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#endif
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