From 23ea941bb512f6f926b58ecacc3757de9d6570fd Mon Sep 17 00:00:00 2001
From: Quentin DECAUNES <le.storm1er@gmail.com>
Date: Thu, 6 Jun 2019 16:32:08 +0200
Subject: [PATCH] Updated ryzenadj to 0.5.2.

---
 bin/libryzenadj.dll | Bin 14848 -> 14848 bytes
 bin/ryzenadj.exe    | Bin 25088 -> 25600 bytes
 bin/ryzenadj.h      | 120 ++++++++++++++++++++++----------------------
 3 files changed, 60 insertions(+), 60 deletions(-)

diff --git a/bin/libryzenadj.dll b/bin/libryzenadj.dll
index f24c32d8676e389a16f9cd8a60d218d9538aea4c..4b5b8fb9d684432bb2bcf800014edc561bd4b7ac 100644
GIT binary patch
delta 32
mcmZoDX(-tsz{osp`H#uMjJ`~fwwsd}A1Q$No86UmiUR=6&kU*n

delta 32
mcmZoDX(-tsz{vb4@%v<9Mqj3P8#gC0K2iYjH@hqC6bAs`8x6ex

diff --git a/bin/ryzenadj.exe b/bin/ryzenadj.exe
index 7c9ba49784bcaf57eb7b5980503b9c5cf2b9d81c..50a4d74f2182eac3af1fb844ad84a37a4e03d56c 100644
GIT binary patch
delta 6829
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diff --git a/bin/ryzenadj.h b/bin/ryzenadj.h
index 5eb2eb1..083474b 100644
--- a/bin/ryzenadj.h
+++ b/bin/ryzenadj.h
@@ -1,60 +1,60 @@
-/* SPDX-License-Identifier: LGPL */
-/* Copyright (C) 2019 Jiaxun Yang <jiaxun.yang@flygoat.com> */
-/* RyzenAdj API */
-
-#ifndef RYZENADJ_H
-#define RYZENADJ_H
-#ifdef __cplusplus
-extern "C" {
-#endif
-#include  "nb_smu_ops.h"
-
-#ifdef _WIN32
-#define EXP __declspec(dllexport)
-#define CALL __stdcall
-#else
-#define EXP
-#define CALL
-#endif
-
-#define RYZENADJ_VER 5
-
-typedef struct {
-	nb_t nb;
-	pci_obj_t pci_obj;
-	smu_t mp1_smu;
-	smu_t psmu;
-} *ryzen_access;
-
-EXP ryzen_access CALL init_ryzenadj();
-
-EXP void CALL cleanup_ryzenadj(ryzen_access ry);
-
-EXP int CALL set_stapm_limit(ryzen_access, uint32_t value);
-EXP int CALL set_fast_limit(ryzen_access, uint32_t value);
-EXP int CALL set_slow_limit(ryzen_access, uint32_t value);
-EXP int CALL set_slow_time(ryzen_access, uint32_t value);
-EXP int CALL set_stapm_time(ryzen_access, uint32_t value);
-EXP int CALL set_tctl_temp(ryzen_access, uint32_t value);
-EXP int CALL set_vrm_current(ryzen_access, uint32_t value);
-EXP int CALL set_vrmsoc_current(ryzen_access, uint32_t value);
-EXP int CALL set_vrmmax_current(ryzen_access, uint32_t value);
-EXP int CALL set_vrmsocmax_current(ryzen_access, uint32_t value);
-EXP int CALL set_psi0_current(ryzen_access, uint32_t value);
-EXP int CALL set_psi0soc_current(ryzen_access, uint32_t value);
-EXP int CALL set_max_gfxclk_freq(ryzen_access, uint32_t value);
-EXP int CALL set_min_gfxclk_freq(ryzen_access, uint32_t value);
-EXP int CALL set_max_socclk_freq(ryzen_access, uint32_t value);
-EXP int CALL set_min_socclk_freq(ryzen_access, uint32_t value);
-EXP int CALL set_max_fclk_freq(ryzen_access, uint32_t value);
-EXP int CALL set_min_fclk_freq(ryzen_access, uint32_t value);
-EXP int CALL set_max_vcn(ryzen_access, uint32_t value);
-EXP int CALL set_min_vcn(ryzen_access, uint32_t value);
-EXP int CALL set_max_lclk(ryzen_access, uint32_t value);
-EXP int CALL set_min_lclk(ryzen_access, uint32_t value);
-
-
-#ifdef __cplusplus
-}
-#endif
-#endif
+/* SPDX-License-Identifier: LGPL */
+/* Copyright (C) 2019 Jiaxun Yang <jiaxun.yang@flygoat.com> */
+/* RyzenAdj API */
+
+#ifndef RYZENADJ_H
+#define RYZENADJ_H
+#ifdef __cplusplus
+extern "C" {
+#endif
+#include  "nb_smu_ops.h"
+
+#ifdef _WIN32
+#define EXP __declspec(dllexport)
+#define CALL __stdcall
+#else
+#define EXP
+#define CALL
+#endif
+
+#define RYZENADJ_VER 5
+
+typedef struct {
+	nb_t nb;
+	pci_obj_t pci_obj;
+	smu_t mp1_smu;
+	smu_t psmu;
+} *ryzen_access;
+
+EXP ryzen_access CALL init_ryzenadj();
+
+EXP void CALL cleanup_ryzenadj(ryzen_access ry);
+
+EXP int CALL set_stapm_limit(ryzen_access, uint32_t value);
+EXP int CALL set_fast_limit(ryzen_access, uint32_t value);
+EXP int CALL set_slow_limit(ryzen_access, uint32_t value);
+EXP int CALL set_slow_time(ryzen_access, uint32_t value);
+EXP int CALL set_stapm_time(ryzen_access, uint32_t value);
+EXP int CALL set_tctl_temp(ryzen_access, uint32_t value);
+EXP int CALL set_vrm_current(ryzen_access, uint32_t value);
+EXP int CALL set_vrmsoc_current(ryzen_access, uint32_t value);
+EXP int CALL set_vrmmax_current(ryzen_access, uint32_t value);
+EXP int CALL set_vrmsocmax_current(ryzen_access, uint32_t value);
+EXP int CALL set_psi0_current(ryzen_access, uint32_t value);
+EXP int CALL set_psi0soc_current(ryzen_access, uint32_t value);
+EXP int CALL set_max_gfxclk_freq(ryzen_access, uint32_t value);
+EXP int CALL set_min_gfxclk_freq(ryzen_access, uint32_t value);
+EXP int CALL set_max_socclk_freq(ryzen_access, uint32_t value);
+EXP int CALL set_min_socclk_freq(ryzen_access, uint32_t value);
+EXP int CALL set_max_fclk_freq(ryzen_access, uint32_t value);
+EXP int CALL set_min_fclk_freq(ryzen_access, uint32_t value);
+EXP int CALL set_max_vcn(ryzen_access, uint32_t value);
+EXP int CALL set_min_vcn(ryzen_access, uint32_t value);
+EXP int CALL set_max_lclk(ryzen_access, uint32_t value);
+EXP int CALL set_min_lclk(ryzen_access, uint32_t value);
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif